The present invention relates generally to integrated circuit device testing techniques and, more particularly, to a method and apparatus for implementing integrated circuit (IC) device testing with improved SPQL (shipped product quality level), reliability and yield performance.
The traditional integrated circuit fabrication process is a series of steps by which a geometric pattern or set of geometric patterns is transformed into an operational integrated circuit. An integrated circuit consists of superimposed layers of conducting, insulating, and device-forming materials. By arranging predetermined geometric shapes in each of these layers, an integrated circuit that performs the desired function may be constructed. The overall fabrication process consists of the patterning of a particular sequence of successive layers.
Defects in integrated circuit structures may be caused by many factors. Some defects are due to imperfections in the underlying semiconductor crystalline structure, while others are caused by imperfections in the physical structure of the circuit components and connections. For instance, a “dislocation” is a physical defect in the structure of the semiconductor crystal (e.g., silicon) at a very small scale. A dislocation may involve as few as four or five silicon atoms oriented differently than the other atoms in the crystal. A dislocation can impair the electrical function of a chip by causing threshold voltage shifts or leakage current. However, due to the nature of most dislocations, a dislocation is not easily detected. Furthermore, since the electrical activity of a dislocation defect can increase with the passage of time/accumulated charge, the continued application of heat and voltage after fabrication can cause circuit failure.
In addition to dislocation type defects mentioned above, other defects may also occur at contact points within a circuit or module. A contact point is the region located at the top or bottom of an opening between layers that allows an electrical contact to be made to individual layers. These contact points may become stressed during the fabrication process and develop an undesirable resistance to the passage of electrical current that may ultimately impede circuit performance. Ideally, these contact points will transmit an electrical current or signal with very little or no resistance. However, as these contact points develop increased resistance, they may eventually prevent the components within an integrated circuit from responding correctly. In an extreme case, a contact point may be so damaged as to create an open circuit, leading to an inoperative circuit or device. Damage to the contact points may be caused by stresses such as heating and cooling.
Another type of defect that can adversely affect circuit performance is what is known as a “stacking fault.” A stacking fault occurs when there are localized partial displacements of closely packed silicon planes that upset the normal crystal lattice structure. Stacking faults are common in integrated circuits and tend to increase as the device density increases. Yet another common defect is what is known as a “high resistance strap.” In general, a strap is a layer of doped polysilicon that is used as an interconnection between components of a chip. A strap may have a constriction or crack in the polysilicon that results in the strap having a higher than normal resistance. Still another known type of defect in integrated circuit devices the existence in micro-cracked metallurgy formed over topographic device features and in via structures.
Each of the various types of manufacturing defects discussed above gives rise to decreased yield, increased “shipped product quality level” or “SPQL” (which is a metric describing the ratio of bad parts shipped to total parts shipped—as discovered by a customer), and increased device failures over time in the field (i.e., decreased reliability). Accordingly, one existing solution to address at least some of these metrics is the implementation of module level burn-in testing, which is designed to find defects in an integrated circuit.
Generally speaking, burn-in testing includes subjecting a circuit to a higher than normal voltage and temperature to stress the circuit components. Burn-in testing can be performed directly in-situ on the wafer, or at a later time such as when the individual integrated circuits have been packaged and incorporated into a finished module, component, or product. For example, once a wafer has been processed, the overall wafer is tested for defects. A probe device is connected to the contact pads for each die located on the periphery or spine of the individual integrated circuits. This allows each integrated circuit to be connected to an electrical source and a reference ground to supply an operational current.
The wafer is typically tested at voltage levels approximately 1.5 times the rated nominal value. For example, a typical circuit on a wafer may be designed to operate with a supplied voltage level of approximately 3.3 volts. Therefore, in this specific example of burn-in testing, the circuit will be operated at a voltage level of approximately 5-6 volts. This enhanced voltage level will create a flow of electricity and enhanced electric fields throughout the circuit which are greater than normal. While this stress is greater than the stress applied to the circuits during normal operations, the applied levels of current and the resulting electrical fields are controlled during burn-in testing so that they will not adversely affect the integrated circuit, but will only trigger defects so that they may be located and eliminated.
During the burn-in testing period, the circuitry on the wafer is electrically “exercised” or tested. However, due to the nature of certain defects, many of the defects listed above may not be readily apparent during standard burn-in testing. This is because the effects of many common defects increase only with the passage of time/accumulated charge, or with the continued application of heat and/or voltage to the affected components. As such, conventional module level burn-in provides limited success at the expense of yield.
Another solution, described by the Applicant of the present application in U.S. Pat. No. 6,114,181 (and assigned to the assignee of the present application) also involves module level burn-in, but in an environment that further simulates a card attach process step into the fabrication process, prior to conventional module burn-in testing. In other words, this technique essentially emulates customer activity by introducing a “thermal bump” step into the burn-in process that simulates the temperature conditions experienced when a chip is attached to a circuit card. In this manner, the thermal bump induces or accelerates the failure of certain weak modules and thus allows for identification of faulty modules during subsequent reliability testing steps, thereby resulting in a reduced SPQL as well as better reliability.
Notwithstanding the above described testing techniques, however, it would be desirable to implement even further improvements in integrated circuit device testing techniques that result in improved SPQL and reliability performance, but also in a manner that maintains/improves yield performance as well.